mirror of https://github.com/YosysHQ/yosys.git
43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
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/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module mac(
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input clk,
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input signed [4:0] in_A,
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input signed [4:0] in_B,
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input signed [4:0] in_D,
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output reg signed [11:0] out_P,
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input srst_P,
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input signed [4:0] casA,
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input signed [4:0] casB
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);
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// sync reset P
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always@(posedge clk) begin
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if (~srst_P) begin
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out_P <= 12'h000;
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end else begin
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out_P <= in_A * (in_B + in_D) + out_P;
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end
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end
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endmodule
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