mirror of https://github.com/YosysHQ/yosys.git
119 lines
2.7 KiB
Verilog
119 lines
2.7 KiB
Verilog
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/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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// See document PolarFire Family Fabric User Guide
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// section 4.2 for port list.
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// Asynchronous read
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module $__uSRAM_AR_ (...);
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parameter INIT = 0;
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parameter ADDR_BITS = 6;
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parameter PORT_W_WIDTH = 12;
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parameter PORT_R_WIDTH = 12;
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parameter PORT_R_USED = 0;
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parameter PORT_W_USED = 0;
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input PORT_W_CLK;
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input [ADDR_BITS-1:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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input PORT_W_WR_EN;
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input [ADDR_BITS-1:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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RAM64x12 _TECHMAP_REPLACE_ (
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.R_ADDR(PORT_R_ADDR),
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.R_ADDR_BYPASS(1'b1),
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.R_ADDR_EN(1'b0),
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.R_ADDR_SL_N(1'b1),
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.R_ADDR_SD(1'b0),
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.R_ADDR_AL_N(1'b1),
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.R_ADDR_AD_N(1'b0),
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.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
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.R_DATA(PORT_R_RD_DATA),
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.R_DATA_BYPASS(1'b1),
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.R_DATA_EN(1'b0),
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.R_DATA_SL_N(1'b1),
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.R_DATA_SD(1'b0),
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.R_DATA_AL_N(1'b1),
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.R_DATA_AD_N(1'b0),
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.W_CLK(PORT_W_CLK),
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.W_ADDR(PORT_W_ADDR),
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.W_DATA(PORT_W_WR_DATA),
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.W_EN(PORT_W_WR_EN),
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.BUSY_FB(1'b0)
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);
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endmodule
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// Synchronous read
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module $__uSRAM_SR_ (...);
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parameter INIT = 0;
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parameter ADDR_BITS = 6;
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parameter PORT_W_WIDTH = 12;
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parameter PORT_R_WIDTH = 12;
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parameter PORT_R_USED = 0;
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parameter PORT_W_USED = 0;
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input PORT_W_CLK;
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input [ADDR_BITS-1:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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input PORT_W_WR_EN;
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// Read port clock and enable signal
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// that async read uSRAM doesn't have
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input PORT_R_CLK;
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input PORT_R_RD_EN;
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input [ADDR_BITS-1:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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RAM64x12 _TECHMAP_REPLACE_ (
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.R_CLK(PORT_R_CLK),
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.R_ADDR(PORT_R_ADDR),
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.R_ADDR_BYPASS(1'b0),
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.R_ADDR_EN(PORT_R_RD_EN),
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.R_ADDR_SL_N(1'b1),
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.R_ADDR_SD(1'b0),
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.R_ADDR_AL_N(1'b1),
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.R_ADDR_AD_N(1'b0),
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.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
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.R_DATA(PORT_R_RD_DATA),
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.R_DATA_BYPASS(1'b1),
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.R_DATA_EN(1'b0),
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.R_DATA_SL_N(1'b1),
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.R_DATA_SD(1'b0),
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.R_DATA_AL_N(1'b1),
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.R_DATA_AD_N(1'b0),
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.W_CLK(PORT_W_CLK),
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.W_ADDR(PORT_W_ADDR),
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.W_DATA(PORT_W_WR_DATA),
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.W_EN(PORT_W_WR_EN),
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.BUSY_FB(1'b0)
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);
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endmodule
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