mirror of https://github.com/YosysHQ/yosys.git
13 lines
207 B
Verilog
13 lines
207 B
Verilog
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module dynslice (
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input clk ,
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input [9:0] ctrl ,
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input [15:0] din ,
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input [3:0] sel ,
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output reg [127:0] dout
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);
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always @(posedge clk)
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begin
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dout[ctrl*sel+:16] <= din ;
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end
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endmodule
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