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13 lines
272 B
Plaintext
13 lines
272 B
Plaintext
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logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
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read_verilog <<EOT
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module top(x);
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generate
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if (1) begin : blk
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output wire x;
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assign x = 1;
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end
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endgenerate
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output wire x;
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endmodule
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EOT
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