2019-04-29 06:38:56 -05:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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2019-04-30 03:51:51 -05:00
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bool did_something;
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2019-10-16 04:40:32 -05:00
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dict<SigBit, State> initbits;
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pool<SigBit> rminitbits;
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2019-04-30 03:51:51 -05:00
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#include "passes/pmgen/peepopt_pm.h"
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2019-10-16 04:40:32 -05:00
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#include "generate.h"
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2019-04-30 03:51:51 -05:00
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2019-04-29 06:38:56 -05:00
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struct PeepoptPass : public Pass {
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PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" peepopt [options] [selection]\n");
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log("\n");
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log("This pass applies a collection of peephole optimizers to the current design.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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2019-10-16 04:40:32 -05:00
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std::string genmode;
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2019-05-03 01:25:30 -05:00
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log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n");
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2019-04-29 06:38:56 -05:00
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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2019-10-16 04:40:32 -05:00
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if (args[argidx] == "-generate" && argidx+1 < args.size()) {
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genmode = args[++argidx];
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continue;
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}
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2019-04-29 06:38:56 -05:00
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break;
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}
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extra_args(args, argidx, design);
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2019-10-16 04:40:32 -05:00
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if (!genmode.empty())
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{
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initbits.clear();
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rminitbits.clear();
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if (genmode == "shiftmul")
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GENERATE_PATTERN(peepopt_pm, shiftmul);
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else if (genmode == "muldiv")
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GENERATE_PATTERN(peepopt_pm, muldiv);
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else if (genmode == "dffmux")
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GENERATE_PATTERN(peepopt_pm, dffmux);
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else
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log_abort();
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return;
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}
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for (auto module : design->selected_modules())
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{
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2019-04-30 03:51:51 -05:00
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did_something = true;
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2019-10-16 04:40:32 -05:00
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while (did_something)
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{
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2019-04-30 03:51:51 -05:00
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did_something = false;
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2019-10-16 04:40:32 -05:00
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initbits.clear();
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rminitbits.clear();
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peepopt_pm pm(module);
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for (auto w : module->wires()) {
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2020-04-02 11:51:32 -05:00
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auto it = w->attributes.find(ID::init);
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2019-10-16 04:40:32 -05:00
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if (it != w->attributes.end()) {
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SigSpec sig = pm.sigmap(w);
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Const val = it->second;
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int len = std::min(GetSize(sig), GetSize(val));
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for (int i = 0; i < len; i++) {
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if (sig[i].wire == nullptr)
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continue;
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if (val[i] != State::S0 && val[i] != State::S1)
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continue;
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initbits[sig[i]] = val[i];
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}
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}
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}
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pm.setup(module->selected_cells());
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2019-04-30 03:51:51 -05:00
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pm.run_shiftmul();
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2019-04-30 04:25:15 -05:00
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pm.run_muldiv();
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2019-09-11 02:56:38 -05:00
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pm.run_dffmux();
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2019-10-16 04:40:32 -05:00
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for (auto w : module->wires()) {
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2020-04-02 11:51:32 -05:00
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auto it = w->attributes.find(ID::init);
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2019-10-16 04:40:32 -05:00
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if (it != w->attributes.end()) {
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SigSpec sig = pm.sigmap(w);
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Const &val = it->second;
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int len = std::min(GetSize(sig), GetSize(val));
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for (int i = 0; i < len; i++) {
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if (rminitbits.count(sig[i]))
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val[i] = State::Sx;
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}
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}
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}
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initbits.clear();
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rminitbits.clear();
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2019-04-30 03:51:51 -05:00
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}
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2019-04-29 06:38:56 -05:00
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}
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}
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} PeepoptPass;
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PRIVATE_NAMESPACE_END
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