yosys/tests/arch/efinix/fsm.ys

16 lines
555 B
Plaintext
Raw Normal View History

2019-10-18 05:19:59 -05:00
read_verilog ../common/fsm.v
2019-10-04 05:42:06 -05:00
hierarchy -top fsm
proc
flatten
2019-11-11 08:41:33 -06:00
equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
2019-10-04 05:42:06 -05:00
cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 6 t:EFX_FF
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D