2019-08-04 04:46:36 -05:00
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module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 8;
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parameter CFG_DBITS = 20;
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2019-08-11 06:59:39 -05:00
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parameter CFG_ENABLE_A = 1;
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2019-08-04 04:46:36 -05:00
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [5119:0] INIT = 5119'bx;
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parameter TRANSP2 = 0;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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input [CFG_DBITS-1:0] A1DATA;
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input [CFG_ENABLE_A-1:0] A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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output [CFG_DBITS-1:0] B1DATA;
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input B1EN;
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localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
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EFX_RAM_5K #(
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2019-08-11 03:46:48 -05:00
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.READ_WIDTH(CFG_DBITS),
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.WRITE_WIDTH(CFG_DBITS),
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2019-08-04 04:46:36 -05:00
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.OUTPUT_REG(1'b0),
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.RCLK_POLARITY(1'b1),
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.RE_POLARITY(1'b1),
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.WCLK_POLARITY(1'b1),
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.WE_POLARITY(1'b1),
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.WCLKE_POLARITY(1'b1),
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.WRITE_MODE(WRITEMODE_A),
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.INIT_0(INIT[ 0*256 +: 256]),
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.INIT_1(INIT[ 1*256 +: 256]),
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.INIT_2(INIT[ 2*256 +: 256]),
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.INIT_3(INIT[ 3*256 +: 256]),
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.INIT_4(INIT[ 4*256 +: 256]),
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.INIT_5(INIT[ 5*256 +: 256]),
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.INIT_6(INIT[ 6*256 +: 256]),
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.INIT_7(INIT[ 7*256 +: 256]),
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.INIT_8(INIT[ 8*256 +: 256]),
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.INIT_9(INIT[ 9*256 +: 256]),
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.INIT_A(INIT[10*256 +: 256]),
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.INIT_B(INIT[11*256 +: 256]),
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.INIT_C(INIT[12*256 +: 256]),
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.INIT_D(INIT[13*256 +: 256]),
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.INIT_E(INIT[14*256 +: 256]),
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.INIT_F(INIT[15*256 +: 256]),
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.INIT_10(INIT[16*256 +: 256]),
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.INIT_11(INIT[17*256 +: 256]),
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.INIT_12(INIT[18*256 +: 256]),
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.INIT_13(INIT[19*256 +: 256])
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) _TECHMAP_REPLACE_ (
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.WDATA(A1DATA),
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.WADDR(A1ADDR),
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.WE(A1EN),
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.WCLK(CLK2),
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.WCLKE(1'b1),
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.RDATA(B1DATA),
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.RADDR(B1ADDR),
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.RE(B1EN),
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.RCLK(CLK3)
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);
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endmodule
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