mirror of https://github.com/YosysHQ/yosys.git
39 lines
661 B
Verilog
39 lines
661 B
Verilog
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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [47:0] P_48;
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DSP48 #(
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// Disable all registers
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.AREG(0),
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.BREG(0),
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.B_INPUT("DIRECT"),
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.CARRYINREG(0),
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.CARRYINSELREG(0),
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.CREG(0),
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.MREG(0),
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.OPMODEREG(0),
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.PREG(0),
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.SUBTRACTREG(0),
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.LEGACY_MODE("MULT18X18")
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) _TECHMAP_REPLACE_ (
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//Data path
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.A(A),
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.B(B),
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.C(48'b0),
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.P(P_48),
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.SUBTRACT(1'b0),
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.OPMODE(7'b000101),
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.CARRYINSEL(2'b00),
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.BCIN(18'b0),
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.PCIN(48'b0),
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.CARRYIN(1'b0)
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);
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assign Y = P_48;
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endmodule
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