mirror of https://github.com/YosysHQ/yosys.git
23 lines
442 B
Bash
23 lines
442 B
Bash
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#!/bin/bash
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set -ex
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for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation
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do
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[ -f $job.ok -a $job.ok -nt $job.tex ] && continue
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if [ -f $job/make.sh ]; then
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cd $job
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bash make.sh
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cd ..
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fi
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old_md5=$([ -f $job.aux ] && md5sum < $job.aux || true)
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while
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pdflatex -shell-escape -halt-on-error $job.tex
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new_md5=$(md5sum < $job.aux)
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[ "$old_md5" != "$new_md5" ]
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do
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old_md5="$new_md5"
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done
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touch $job.ok
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done
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