mirror of https://github.com/YosysHQ/yosys.git
23 lines
362 B
Plaintext
23 lines
362 B
Plaintext
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read_rtlil <<EOT
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module \m
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wire width 1 \w
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process $p
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switch 3'001
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case 3'--1
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assign \w 3'001
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case 3'-1-
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assign \w 3'010
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case 3'1--
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assign \w 3'100
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end
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end
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end
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EOT
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proc_clean # Bug: removes the cases.
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proc_clean # Removes the now-empty switch and its containing process.
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select -assert-count 1 */p:*
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