2018-07-13 07:52:25 -05:00
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2019-08-27 07:07:06 -05:00
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OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \
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techlibs/ecp5/ecp5_gsr.o
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2018-07-13 07:52:25 -05:00
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2019-08-30 05:05:09 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
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2018-07-13 07:52:25 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
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2018-10-21 13:27:02 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
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2019-07-16 15:44:55 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
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Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 06:30:00 -06:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt))
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2018-10-10 10:35:19 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
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Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 06:30:00 -06:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
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2018-07-13 08:46:12 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
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2018-10-18 13:39:48 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
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2019-07-08 09:40:12 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
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2018-10-09 08:19:04 -05:00
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2019-10-04 13:04:10 -05:00
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
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$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
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2019-06-14 06:02:12 -05:00
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2018-10-10 10:35:19 -05:00
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EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
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.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
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2018-10-09 08:19:04 -05:00
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techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
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$(Q) mkdir -p techlibs/ecp5
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2019-10-19 01:04:52 -05:00
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$(P) $(PYTHON_EXECUTABLE) $<
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2018-10-09 08:19:04 -05:00
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$(Q) touch $@
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2018-10-10 10:35:19 -05:00
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techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py
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$(Q) mkdir -p techlibs/ecp5
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2019-10-19 01:04:52 -05:00
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$(P) $(PYTHON_EXECUTABLE) $<
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2018-10-10 10:35:19 -05:00
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$(Q) touch $@
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2018-10-09 08:19:04 -05:00
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techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk
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techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk
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2018-10-10 10:35:19 -05:00
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techlibs/ecp5/bram_conn_1.vh: techlibs/ecp5/brams_connect.mk
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techlibs/ecp5/bram_conn_2.vh: techlibs/ecp5/brams_connect.mk
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techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
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techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
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techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
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2019-10-01 07:46:36 -05:00
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techlibs/ecp5/bram_conn_36.vh: techlibs/ecp5/brams_connect.mk
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2018-10-10 10:35:19 -05:00
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2018-12-28 10:21:53 -06:00
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
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2019-10-01 07:46:36 -05:00
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$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_36.vh))
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