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yosys/techlibs/coolrunner2/Makefile.inc

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coolrunner2: Initial commit
2017-06-24 08:59:20 -05:00
OBJS += techlibs/coolrunner2/synth_coolrunner2.o
coolrunner2: Initial techmapping for $sop
2017-06-24 10:51:24 -05:00
OBJS += techlibs/coolrunner2/coolrunner2_sop.o
coolrunner2: Initial commit
2017-06-24 08:59:20 -05:00
coolrunner2: Initial mapping of latches
2017-06-25 22:58:45 -05:00
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
coolrunner2: Initial commit
2017-06-24 08:59:20 -05:00
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
coolrunner2: Initial mapping of DFFs All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)
2017-06-25 22:16:43 -05:00
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))