yosys/tests/sat/sizebits.ys

read_verilog -sv sizebits.sv
prep; async2sync; sat -verify -prove-asserts
Allow $size and $bits in verilog mode, actually check test case 2017-09-29 04:56:43 -05:00			`read_verilog -sv sizebits.sv`
tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions. 2024-01-22 10:44:05 -06:00			`prep; async2sync; sat -verify -prove-asserts`