mirror of https://github.com/YosysHQ/yosys.git
65 lines
1.1 KiB
Verilog
65 lines
1.1 KiB
Verilog
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`default_nettype none
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module sram1024x18 (
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clk_a,
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cen_a,
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wen_a,
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addr_a,
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wmsk_a,
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wdata_a,
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rdata_a,
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clk_b,
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cen_b,
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wen_b,
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addr_b,
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wmsk_b,
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wdata_b,
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rdata_b
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);
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parameter [1024*18-1:0] init = 18431'bx;
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(* clkbuf_sink *)
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input wire clk_a;
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input wire cen_a;
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input wire wen_a;
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input wire [9:0] addr_a;
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input wire [17:0] wmsk_a;
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input wire [17:0] wdata_a;
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output reg [17:0] rdata_a;
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(* clkbuf_sink *)
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input wire clk_b;
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input wire cen_b;
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input wire wen_b;
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input wire [9:0] addr_b;
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input wire [17:0] wmsk_b;
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input wire [17:0] wdata_b;
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output reg [17:0] rdata_b;
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reg [17:0] ram [1023:0];
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integer i;
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initial begin
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for (i = 0; i < 1024; i = i + 1) begin
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ram[i] = init[18*i +: 18];
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end
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end
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always @(posedge clk_a) begin
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if (!cen_a) begin
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if (!wen_a)
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for (i = 0; i < 18; i++) begin
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if (!wmsk_a[i]) ram[addr_a][i] <= wdata_a[i];
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end
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rdata_a <= ram[addr_a];
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end
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end
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always @(posedge clk_b) begin
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if (!cen_b) begin
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if (!wen_b)
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for (i = 0; i < 18; i++) begin
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if (!wmsk_b[i]) ram[addr_b][i] <= wdata_b[i];
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end
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rdata_b <= ram[addr_b];
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end
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end
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endmodule
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