mirror of https://github.com/YosysHQ/yosys.git
95 lines
2.4 KiB
Plaintext
95 lines
2.4 KiB
Plaintext
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pattern xilinx_dsp_cascade
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigSpec> sigC
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code
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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endcode
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match dsp_pcin
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select dsp_pcin->type.in(\DSP48E1)
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select !param(dsp_pcin, \CREG, State::S1).as_bool()
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select port(dsp_pcin, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(dsp_pcin, \C, SigSpec())) > 1
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select nusers(port(dsp_pcin, \PCIN, SigSpec())) == 0
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endmatch
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code sigC
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sigC = unextend(port(dsp_pcin, \C));
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endcode
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match dsp_pcout
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select dsp_pcout->type.in(\DSP48E1)
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select nusers(port(dsp_pcout, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout, \PCOUT, SigSpec())) <= 1
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index <SigSpec> port(dsp_pcout, \P)[0] === sigC[0]
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filter GetSize(port(dsp_pcin, \P)) >= GetSize(sigC)
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filter port(dsp_pcout, \P).extract(0, GetSize(sigC)) == sigC
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optional
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endmatch
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match dsp_pcout_shift17
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if !dsp_pcout
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select dsp_pcout_shift17->type.in(\DSP48E1)
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select nusers(port(dsp_pcout_shift17, \P, SigSpec())) > 1
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select nusers(port(dsp_pcout_shift17, \PCOUT, SigSpec())) <= 1
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index <SigSpec> port(dsp_pcout_shift17, \P)[17] === sigC[0]
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filter GetSize(port(dsp_pcout_shift17, \P)) >= GetSize(sigC)+17
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filter port(dsp_pcout_shift17, \P).extract(17, GetSize(sigC)) == sigC
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endmatch
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code
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Cell *dsp;
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if (dsp_pcout)
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dsp = dsp_pcout;
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else if (dsp_pcout_shift17)
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dsp = dsp_pcout_shift17;
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else log_abort();
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dsp_pcin->setPort(ID(C), Const(0, 48));
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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SigSpec opmode = param(dsp_pcin, \OPMODE, Const(0, 7));
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if (dsp_pcout)
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opmode[6] = State::S0;
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else if (dsp_pcout_shift17)
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opmode[6] = State::S1;
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else log_abort();
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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dsp_pcin->setPort(ID(OPMODE), opmode);
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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if (nusers(port(dsp_pcin, \PCOUT, SigSpec())) > 1) {
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log_debug(" Saturated PCIN/PCOUT on %s\n", log_id(dsp_pcin));
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blacklist(dsp_pcin);
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}
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if (nusers(port(dsp, \PCIN, SigSpec())) > 1) {
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log_debug(" Saturated PCIN/PCOUT on %s\n", log_id(dsp));
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blacklist(dsp_pcout);
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}
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accept;
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endcode
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