mirror of https://github.com/YosysHQ/yosys.git
13 lines
497 B
Plaintext
13 lines
497 B
Plaintext
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read_verilog tribuf.v
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
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select -assert-count 1 t:$_TBUF_
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select -assert-none t:$_TBUF_ %% t:* %D
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