yosys/tests/arch/anlogic/latches.ys

read_verilog latches.v
design -save read

hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3

select -assert-none t:AL_MAP_LUT3 %% t:* %D


design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3

select -assert-none t:AL_MAP_LUT3 %% t:* %D


design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT5

select -assert-none t:AL_MAP_LUT5 %% t:* %D
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`read_verilog latches.v`
			`design -save read`

split latches into separate checks 2019-10-04 04:08:42 -05:00			`hierarchy -top latchp`
hierarchy - proc reorder 2019-10-18 02:06:43 -05:00			`proc`
split latches into separate checks 2019-10-04 04:08:42 -05:00			`# Can't run any sort of equivalence check because latches are blown to LUTs`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`synth_anlogic`
split latches into separate checks 2019-10-04 04:08:42 -05:00			`cd latchp # Constrain all select calls below inside the top module`
			`select -assert-count 1 t:AL_MAP_LUT3`

			`select -assert-none t:AL_MAP_LUT3 %% t:* %D`


			`design -load read`
			`hierarchy -top latchn`
hierarchy - proc reorder 2019-10-18 02:06:43 -05:00			`proc`
split latches into separate checks 2019-10-04 04:08:42 -05:00			`# Can't run any sort of equivalence check because latches are blown to LUTs`
			`synth_anlogic`
			`cd latchn # Constrain all select calls below inside the top module`
			`select -assert-count 1 t:AL_MAP_LUT3`

			`select -assert-none t:AL_MAP_LUT3 %% t:* %D`

Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00
			`design -load read`
split latches into separate checks 2019-10-04 04:08:42 -05:00			`hierarchy -top latchsr`
hierarchy - proc reorder 2019-10-18 02:06:43 -05:00			`proc`
split latches into separate checks 2019-10-04 04:08:42 -05:00			`# Can't run any sort of equivalence check because latches are blown to LUTs`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`synth_anlogic`
split latches into separate checks 2019-10-04 04:08:42 -05:00			`cd latchsr # Constrain all select calls below inside the top module`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`select -assert-count 1 t:AL_MAP_LUT5`
split latches into separate checks 2019-10-04 04:08:42 -05:00
			`select -assert-none t:AL_MAP_LUT5 %% t:* %D`