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yosys/tests/proc/proc_rom.ys

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Add proc_rom pass.
2022-05-12 16:36:28 -05:00
read_verilog << EOT
module top(input [3:0] a, input en, output [7:0] d);
always @*
if (en)
case(a)
4'h0: d <= 8'h12;
4'h1: d <= 8'h34;
4'h2: d <= 8'h56;
4'h3: d <= 8'h78;
4'h4: d <= 8'h9a;
4'h5: d <= 8'hbc;
4'h6: d <= 8'hde;
4'h7: d <= 8'hff;
4'h8: d <= 8'h61;
4'h9: d <= 8'h49;
4'ha: d <= 8'h36;
4'hb: d <= 8'h81;
4'hc: d <= 8'h8c;
4'hd: d <= 8'ha9;
4'he: d <= 8'h99;
4'hf: d <= 8'h51;
endcase
else
d <= 0;
endmodule
EOT
hierarchy -auto-top
design -save orig
proc
proc_rom: test src attribute on memories
2024-07-25 15:09:13 -05:00
select -assert-count 1 t:$memrd_v2 a:src %i
Add proc_rom pass.
2022-05-12 16:36:28 -05:00
memory
opt_dff
design -stash postopt
design -load orig
proc -norom
design -stash preopt
equiv_opt -assert -run prepare: dummy
proc_rom: Add special handling of const-0 address bits.
2022-05-18 01:18:13 -05:00
design -reset
read_verilog << EOT
module top(input [3:0] a, input en, output [7:0] d);
always @*
if (en)
case(a)
4'h0: d <= 8'h12;
4'h1: d <= 8'h34;
4'h2: d <= 8'h56;
4'h3: d <= 8'h78;
4'h4: d <= 8'h9a;
4'h5: d <= 8'hbc;
4'h6: d <= 8'hde;
4'h7: d <= 8'hff;
4'h8: d <= 8'h61;
4'h9: d <= 8'h49;
4'ha: d <= 8'h36;
4'hb: d <= 8'h81;
4'hc: d <= 8'h8c;
default: d <= 8'h11;
endcase
else
d <= 0;
endmodule
EOT
hierarchy -auto-top
design -save orig
proc
proc_rom: test src attribute on memories
2024-07-25 15:09:13 -05:00
select -assert-count 1 t:$memrd_v2 a:src %i
proc_rom: Add special handling of const-0 address bits.
2022-05-18 01:18:13 -05:00
memory
opt_dff
design -stash postopt
design -load orig
proc -norom
design -stash preopt
equiv_opt -assert -run prepare: dummy
design -reset
read_verilog << EOT
module top(input [31:0] a, input en, output [7:0] d);
always @*
if (en)
case(a)
0: d <= 8'h12;
1: d <= 8'h34;
2: d <= 8'h56;
3: d <= 8'h78;
4: d <= 8'h9a;
5: d <= 8'hbc;
6: d <= 8'hde;
7: d <= 8'hff;
8: d <= 8'h61;
9: d <= 8'h49;
10: d <= 8'h36;
11: d <= 8'h81;
12: d <= 8'h8c;
default: d <= 8'h11;
endcase
else
d <= 0;
endmodule
EOT
hierarchy -auto-top
design -save orig
proc
proc_rom: test src attribute on memories
2024-07-25 15:09:13 -05:00
select -assert-count 1 t:$memrd_v2 a:src %i
proc_rom: Add special handling of const-0 address bits.
2022-05-18 01:18:13 -05:00
memory
opt_dff
design -stash postopt
design -load orig
proc -norom
design -stash preopt
equiv_opt -assert -run prepare: dummy
design -reset
read_verilog << EOT
module top(input [3:0] a, input en, output [7:0] d);
always @*
if (en)
case(a)
'h0: d <= 8'h12;
'h1: d <= 8'h34;
'h2: d <= 8'h56;
'h3: d <= 8'h78;
'h4: d <= 8'h9a;
'h5: d <= 8'hbc;
'h6: d <= 8'hde;
'h7: d <= 8'hff;
'h8: d <= 8'h61;
'h9: d <= 8'h49;
'ha: d <= 8'h36;
'hb: d <= 8'h81;
'hc: d <= 8'h8c;
'hd: d <= 8'ha9;
'he: d <= 8'h99;
'hf: d <= 8'h51;
endcase
else
d <= 0;
endmodule
EOT
hierarchy -auto-top
design -save orig
proc
proc_rom: test src attribute on memories
2024-07-25 15:09:13 -05:00
select -assert-count 1 t:$memrd_v2 a:src %i
proc_rom: Add special handling of const-0 address bits.
2022-05-18 01:18:13 -05:00
memory
opt_dff
design -stash postopt
design -load orig
proc -norom
design -stash preopt
equiv_opt -assert -run prepare: dummy
proc_rom: don't assert on big actionless switch. See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with: ERROR: Assert `width != 0' failed in kernel/mem.cc:518. Ensure we don't proceed if there's nothing to encode.
2024-02-17 08:30:28 -06:00
design -reset
Remove references to ilang
2024-11-04 17:36:31 -06:00
read_rtlil <<EOT
proc_rom: don't assert on big actionless switch. See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with: ERROR: Assert `width != 0' failed in kernel/mem.cc:518. Ensure we don't proceed if there's nothing to encode.
2024-02-17 08:30:28 -06:00
module \m
wire width 3 input 1 \a
process \p
switch \a
case 3'000
case 3'001
case 3'010
case 3'011
case 3'100
case 3'101
case 3'110
case 3'111
end
end
end
EOT
proc_rom: Add special handling of const-0 address bits.
2022-05-18 01:18:13 -05:00
proc_rom: don't assert on big actionless switch. See the test case. PROC_ROM will consider this for evaluation, even though -- without any actions -- lhs is empty (but still "uniform"). A zero-width memory is constructed, which later fails check with: ERROR: Assert `width != 0' failed in kernel/mem.cc:518. Ensure we don't proceed if there's nothing to encode.
2024-02-17 08:30:28 -06:00
proc_rom