mirror of https://github.com/YosysHQ/yosys.git
61 lines
3.0 KiB
Verilog
61 lines
3.0 KiB
Verilog
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// The MLAB
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// --------
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// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
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// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
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// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
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// the memory the ALM uses to store the look-up table data for general usage,
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// producing a 32 address by 20-bit block of memory. MLABs are spread out
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// around the chip, so they can be placed near where they are needed, rather than
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// being comparatively limited in placement for a deep but narrow memory such as
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// the M10K memory block.
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//
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// MLABs are used mainly for shallow but wide memories, such as CPU register
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// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))
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// or shift registers (by using the output of the Nth bit as input for the N+1th
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// bit).
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//
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// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
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// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
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// to put these cells in the same MLAB during cell placement. Because of this
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// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
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// 20 of them represent a physical MLAB.
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//
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// How the MLAB works
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// ------------------
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// MLABs are poorly documented, so the following information is based mainly
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// on the simulation model and my knowledge of how memories like these work.
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// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated
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// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
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// `techmap` just for the sake of renaming the cell ports.
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//
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// The MLAB can be initialised to any value, but unfortunately Quartus only
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// allows memory initialisation from a file. Since Yosys doesn't preserve input
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// file information, or write the contents of an `initial` block to a file,
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// Yosys can't currently initialise the MLAB in a way Quartus will accept.
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//
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// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
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// is high, writes it to the address in A1ADDR. A1EN can therefore be used to
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// conditionally write data to the MLAB.
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//
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// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
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// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
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// then the output can be fed to embedded flops. Presently, Yosys assumes
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// Quartus will pack external flops into the MLAB, but this is an assumption
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// that needs testing.
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// The vendor sim model outputs 'x for a very short period (a few
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// combinational delta cycles) after each write. This has been omitted from
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// the following model because it's very difficult to trigger this in practice
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// as clock cycles will be much longer than any potential blip of 'x, so the
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// model can be treated as always returning a defined result.
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module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
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reg [31:0] mem = 32'b0;
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always @(posedge CLK1)
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if (A1EN) mem[A1ADDR] <= A1DATA;
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assign B1DATA = mem[B1ADDR];
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endmodule
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