mirror of https://github.com/YosysHQ/yosys.git
59 lines
1.5 KiB
Plaintext
59 lines
1.5 KiB
Plaintext
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read_verilog -icells <<EOT
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module top(input C, D, S, R, output [9:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
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assign Q[9:5] = ~Q[4:0];
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endmodule
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EOT
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simplemap
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design -save orig
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#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
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#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
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dfflibmap -prepare -liberty dfflibmap.lib
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equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
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design -load orig
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dfflibmap -liberty dfflibmap.lib
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clean
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select -assert-count 4 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr
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select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -prepare -liberty dfflibmap.lib
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select -assert-count 9 t:$_NOT_
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select -assert-count 1 t:$_DFF_N_
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select -assert-count 4 t:$_DFFSR_PPP_
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select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -map-only -liberty dfflibmap.lib
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select -assert-count 5 t:$_NOT_
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select -assert-count 0 t:dffn
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select -assert-count 1 t:dffsr
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design -load orig
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dfflibmap -prepare -liberty dfflibmap.lib
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dfflibmap -map-only -liberty dfflibmap.lib
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clean
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select -assert-count 4 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr
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select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
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