2019-10-18 05:19:59 -05:00
|
|
|
read_verilog ../common/add_sub.v
|
2019-09-03 03:53:37 -05:00
|
|
|
hierarchy -top top
|
2019-10-18 02:04:02 -05:00
|
|
|
proc
|
2019-09-03 03:53:37 -05:00
|
|
|
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
|
|
|
cd top # Constrain all select calls below inside the top module
|
|
|
|
|
select -assert-count 10 t:LUT4
|
|
|
|
|
select -assert-none t:LUT4 %% t:* %D
|
|
|
|
|
|
