mirror of https://github.com/YosysHQ/yosys.git
42 lines
465 B
Verilog
42 lines
465 B
Verilog
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module FTCP (C, PRE, CLR, T, Q);
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input C, PRE, CLR, T;
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output wire Q;
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wire xorout;
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$_XOR_ xorgate (
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.A(T),
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.B(Q),
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.Y(xorout),
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);
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$_DFFSR_PPP_ dff (
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.C(C),
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.D(xorout),
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.Q(Q),
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.S(PRE),
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.R(CLR),
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);
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endmodule
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module FTCP_N (C, PRE, CLR, T, Q);
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input C, PRE, CLR, T;
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output wire Q;
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wire xorout;
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$_XOR_ xorgate (
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.A(T),
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.B(Q),
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.Y(xorout),
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);
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$_DFFSR_NPP_ dff (
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.C(C),
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.D(xorout),
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.Q(Q),
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.S(PRE),
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.R(CLR),
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);
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endmodule
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