mirror of https://github.com/YosysHQ/yosys.git
17 lines
454 B
Plaintext
17 lines
454 B
Plaintext
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read_verilog latches.v
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design -save read
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proc
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async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
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flatten
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synth_ecp5
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equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load read
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synth_ecp5
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cd top
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select -assert-count 4 t:LUT4
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select -assert-count 1 t:PFUMX
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select -assert-none t:LUT4 t:PFUMX %% t:* %D
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