mirror of https://github.com/YosysHQ/yosys.git
28 lines
533 B
Plaintext
28 lines
533 B
Plaintext
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# read design
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read_verilog counter.v
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hierarchy -check -top counter
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show -notitle -format dot -prefix counter_00
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# the high-level stuff
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proc; opt; memory; opt; fsm; opt
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show -notitle -format dot -prefix counter_01
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# mapping to internal cell library
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techmap; opt
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splitnets -ports;;
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show -notitle -format dot -prefix counter_02
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# mapping flip-flops to mycells.lib
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dfflibmap -liberty mycells.lib
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# mapping logic to mycells.lib
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abc -liberty mycells.lib
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# cleanup
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clean
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show -notitle -lib mycells.v -format dot -prefix counter_03
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