mirror of https://github.com/YosysHQ/yosys.git
52 lines
1.1 KiB
Coq
52 lines
1.1 KiB
Coq
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module LUT1(output F, input I0);
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parameter [1:0] INIT = 0;
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assign F = I0 ? INIT[1] : INIT[0];
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endmodule
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module LUT2(output F, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module LUT3(output F, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4(output F, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module DFF (output reg Q, input CLK, D);
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always @(posedge C)
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Q <= D;
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endmodule
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module DFFN (output reg Q, input CLK, D);
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always @(negedge C)
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Q <= D;
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endmodule
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module VCC(output V);
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assign V = 1;
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endmodule
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module GND(output G);
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assign G = 0;
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endmodule
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module IBUF(output O, input I);
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assign O = I;
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endmodule
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module OBUF(output O, input I);
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assign O = I;
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endmodule
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