riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/techlibs/gowin
History
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
..
Makefile.inc Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
cells_map.v Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
cells_sim.v Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
synth_gowin.cc Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00