mirror of https://github.com/YosysHQ/yosys.git
23 lines
390 B
Verilog
23 lines
390 B
Verilog
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module bar(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire inp;
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output reg out;
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always @(posedge clk)
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if (rst) out <= 1'd0;
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else out <= ~inp;
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endmodule
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module foo(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire inp;
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output wire out;
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(* my_module_instance = 99 *)
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bar bar_instance (clk, rst, inp, out);
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endmodule
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