mirror of https://github.com/YosysHQ/yosys.git
9 lines
161 B
Verilog
9 lines
161 B
Verilog
|
module muliply (a,product);
|
||
|
input [3:0] a;
|
||
|
output [4:0] product;
|
||
|
wire [4:0] product;
|
||
|
|
||
|
assign product = a << 1;
|
||
|
|
||
|
endmodule
|