mirror of https://github.com/YosysHQ/yosys.git
115 lines
2.9 KiB
Verilog
115 lines
2.9 KiB
Verilog
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module fsm_full(
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clock , // Clock
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reset , // Active high reset
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req_0 , // Active high request from agent 0
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req_1 , // Active high request from agent 1
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req_2 , // Active high request from agent 2
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req_3 , // Active high request from agent 3
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gnt_0 , // Active high grant to agent 0
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gnt_1 , // Active high grant to agent 1
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gnt_2 , // Active high grant to agent 2
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gnt_3 // Active high grant to agent 3
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);
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// Port declaration here
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input clock ; // Clock
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input reset ; // Active high reset
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input req_0 ; // Active high request from agent 0
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input req_1 ; // Active high request from agent 1
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input req_2 ; // Active high request from agent 2
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input req_3 ; // Active high request from agent 3
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output gnt_0 ; // Active high grant to agent 0
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output gnt_1 ; // Active high grant to agent 1
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output gnt_2 ; // Active high grant to agent 2
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output gnt_3 ; // Active high grant to agent
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// Internal Variables
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reg gnt_0 ; // Active high grant to agent 0
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reg gnt_1 ; // Active high grant to agent 1
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reg gnt_2 ; // Active high grant to agent 2
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reg gnt_3 ; // Active high grant to agent
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parameter [2:0] IDLE = 3'b000;
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parameter [2:0] GNT0 = 3'b001;
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parameter [2:0] GNT1 = 3'b010;
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parameter [2:0] GNT2 = 3'b011;
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parameter [2:0] GNT3 = 3'b100;
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reg [2:0] state, next_state;
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always @ (state or req_0 or req_1 or req_2 or req_3)
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begin
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next_state = 0;
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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next_state = GNT0;
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end else if (req_1 == 1'b1) begin
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next_state= GNT1;
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end else if (req_2 == 1'b1) begin
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next_state= GNT2;
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end else if (req_3 == 1'b1) begin
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next_state= GNT3;
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end else begin
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next_state = IDLE;
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end
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GNT0 : if (req_0 == 1'b0) begin
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next_state = IDLE;
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end else begin
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next_state = GNT0;
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end
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GNT1 : if (req_1 == 1'b0) begin
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next_state = IDLE;
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end else begin
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next_state = GNT1;
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end
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GNT2 : if (req_2 == 1'b0) begin
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next_state = IDLE;
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end else begin
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next_state = GNT2;
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end
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GNT3 : if (req_3 == 1'b0) begin
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next_state = IDLE;
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end else begin
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next_state = GNT3;
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end
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default : next_state = IDLE;
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endcase
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end
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always @ (posedge clock)
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begin : OUTPUT_LOGIC
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if (reset) begin
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gnt_0 <= 1'b0;
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gnt_1 <= 1'b0;
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gnt_2 <= 1'b0;
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gnt_3 <= 1'b0;
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state <= IDLE;
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end else begin
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state <= next_state;
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case(state)
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IDLE : begin
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gnt_0 <= 1'b0;
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gnt_1 <= 1'b0;
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gnt_2 <= 1'b0;
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gnt_3 <= 1'b0;
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end
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GNT0 : begin
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gnt_0 <= 1'b1;
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end
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GNT1 : begin
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gnt_1 <= 1'b1;
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end
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GNT2 : begin
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gnt_2 <= 1'b1;
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end
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GNT3 : begin
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gnt_3 <= 1'b1;
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end
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default : begin
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state <= IDLE;
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end
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endcase
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end
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end
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endmodule
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