mirror of https://github.com/YosysHQ/yosys.git
9 lines
141 B
Verilog
9 lines
141 B
Verilog
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module bus_con (a,b, y);
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input [3:0] a, b;
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output [7:0] y;
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wire [7:0] y;
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assign y = {a,b};
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endmodule
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