mirror of https://github.com/YosysHQ/yosys.git
12 lines
175 B
Verilog
12 lines
175 B
Verilog
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module always_example();
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reg clk,reset,enable,q_in,data;
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always @ (posedge clk)
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if (reset) begin
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data <= 0;
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end else if (enable) begin
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data <= q_in;
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end
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endmodule
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