mirror of https://github.com/YosysHQ/yosys.git
25 lines
382 B
Verilog
25 lines
382 B
Verilog
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module addbit (
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a , // first input
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b , // Second input
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ci , // Carry input
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sum , // sum output
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co // carry output
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);
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//Input declaration
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input a;
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input b;
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input ci;
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//Ouput declaration
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output sum;
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output co;
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//Port Data types
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wire a;
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wire b;
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wire ci;
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wire sum;
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wire co;
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//Code starts here
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assign {co,sum} = a + b + ci;
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endmodule // End of Module addbit
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