yosys/tests/ice40/memory.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog memory.v
synth_ice40
cd top
select -assert-count 1 t:SB_RAM40_4K
write_verilog memory_synth.v
Fix all comments from PR 2019-08-21 13:52:07 -05:00			`read_verilog memory.v`
Add new tests for ice40 architecture 2019-08-19 23:50:05 -05:00			`synth_ice40`
Remove tech independent synthesis 2019-08-22 14:30:49 -05:00			`cd top`
Fix all comments from PR 2019-08-21 13:52:07 -05:00			`select -assert-count 1 t:SB_RAM40_4K`
			`write_verilog memory_synth.v`