yosys/tests/ice40/memory.ys

5 lines
100 B
Plaintext
Raw Normal View History

2019-08-21 13:52:07 -05:00
read_verilog memory.v
2019-08-19 23:50:05 -05:00
synth_ice40
2019-08-21 13:52:07 -05:00
select -assert-count 1 t:SB_RAM40_4K
write_verilog memory_synth.v