riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/ice40/memory.ys

5 lines
100 B
Plaintext
Raw Blame History

read_verilog memory.v
synth_ice40
select -assert-count 1 t:SB_RAM40_4K
write_verilog memory_synth.v
Reference in New Issue View Git Blame Copy Permalink