mirror of https://github.com/YosysHQ/yosys.git
9 lines
153 B
Verilog
9 lines
153 B
Verilog
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module adffe( input d, clk, rst, en, output reg q );
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always @( posedge clk, posedge rst )
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if (rst)
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q <= 0;
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else
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if (en)
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q <= d;
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endmodule
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