mirror of https://github.com/YosysHQ/yosys.git
24 lines
294 B
Plaintext
24 lines
294 B
Plaintext
|
read_verilog memory_word_as_index.v
|
||
|
|
|
||
|
|
hierarchy
|
||
|
|
proc
|
||
|
|
memory
|
||
|
|
flatten
|
||
|
|
opt -full
|
||
|
|
|
||
|
|
equiv_make gold gate1 equiv
|
||
|
|
equiv_simple
|
||
|
|
equiv_status -assert
|
||
|
|
|
||
|
|
delete equiv
|
||
|
|
|
||
|
|
equiv_make gold gate2 equiv
|
||
|
|
equiv_simple
|
||
|
|
equiv_status -assert
|
||
|
|
|
||
|
|
delete equiv
|
||
|
|
|
||
|
|
equiv_make gold gate3 equiv
|
||
|
|
equiv_simple
|
||
|
|
equiv_status -assert
|