mirror of https://github.com/YosysHQ/yosys.git
4 lines
131 B
Verilog
4 lines
131 B
Verilog
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module \$__EFX_GBUF (input I, output O);
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EFX_GBUFCE #(.CE_POLARITY(1'b1)) _TECHMAP_REPLACE_ (.I(I), .O(O), .CE(1'b1));
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endmodule
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