mirror of https://github.com/YosysHQ/yosys.git
76 lines
893 B
Verilog
76 lines
893 B
Verilog
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`timescale 1ns/1ns
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module tb_aldffe();
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reg clk = 0;
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reg aload = 0;
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reg [0:3] d = 4'b0000;
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reg [0:3] ad = 4'b1010;
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reg en = 0;
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wire [0:3] q;
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aldffe uut(.clk(clk),.d(d),.ad(ad),.aload(aload),.en(en),.q(q));
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always
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#(5) clk <= !clk;
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initial
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begin
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$dumpfile("tb_aldffe");
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$dumpvars(0,tb_aldffe);
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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aload = 1;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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aload = 0;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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en = 1;
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aload = 1;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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aload = 0;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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d = 4'b1100;
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#10
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d = 4'b0011;
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#10
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$finish;
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end
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endmodule
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