mirror of https://github.com/YosysHQ/yosys.git
28 lines
630 B
Verilog
28 lines
630 B
Verilog
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module test(
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input WR1_CLK, WR2_CLK,
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input WR1_WEN, WR2_WEN,
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input [7:0] WR1_ADDR, WR2_ADDR,
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input [7:0] WR1_DATA, WR2_DATA,
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input RD1_CLK, RD2_CLK,
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input [7:0] RD1_ADDR, RD2_ADDR,
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output reg [7:0] RD1_DATA, RD2_DATA
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);
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reg [7:0] memory [0:255];
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always @(posedge WR1_CLK)
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if (WR1_WEN)
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memory[WR1_ADDR] <= WR1_DATA;
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always @(posedge WR2_CLK)
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if (WR2_WEN)
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memory[WR2_ADDR] <= WR2_DATA;
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always @(posedge RD1_CLK)
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RD1_DATA <= memory[RD1_ADDR];
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always @(posedge RD2_CLK)
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RD2_DATA <= memory[RD2_ADDR];
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endmodule
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