yosys/btor.ys

#design should be loaded before executing 

#high level synthesis
#################
#converting processes to cells
proc; 
opt; opt_const -mux_undef; opt;
rename -hide;;;
#converting pmux to mux
techmap -map techlibs/common/pmux2mux.v;
opt;
#converting asyn memory write to syn memory
memory_dff; 
opt;
#flatten design
flatten;;;
#cell output to be a single wire
splitnets -driver;
opt;;;
#writing btor
write_btor design.btor;