mirror of https://github.com/YosysHQ/yosys.git
21 lines
375 B
Plaintext
21 lines
375 B
Plaintext
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#design should be loaded before executing
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#high level synthesis
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#################
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#converting processes to cells
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proc;
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opt;
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#converting pmux to mux
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techmap -map techlibs/common/pmux2mux.v;
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opt;
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#converting asyn memory write to syn memory
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memory_dff;
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opt;
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#flatten design
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flatten;
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opt;
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#adding temporary wires for cell ports
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scatter;
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#writing btor
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write_btor design.btor;
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