yosys/tests/verilog/doubleslash.ys

read_verilog -sv <<EOT
module doubleslash
  (input  logic   a,
   input  logic   b,
   output logic   z);

  logic \a//b ;

  assign \a//b = a & b;
  assign z = ~\a//b ;

endmodule : doubleslash
EOT

hierarchy
proc
opt -full

write_verilog doubleslash.v
design -reset
read_verilog doubleslash.v
preprocessor: do not destroy double slash escaped identifiers The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* / comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase. 2021-08-25 14:34:26 -05:00			`read_verilog -sv <<EOT`
			`module doubleslash`
			`(input logic a,`
			`input logic b,`
			`output logic z);`

			`logic \a//b ;`

			`assign \a//b = a & b;`
			`assign z = ~\a//b ;`

			`endmodule : doubleslash`
			`EOT`

			`hierarchy`
			`proc`
			`opt -full`

			`write_verilog doubleslash.v`
fixup verilog doubleslash test - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again 2021-12-30 01:06:23 -06:00			`design -reset`
			`read_verilog doubleslash.v`