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20 lines
254 B
Plaintext
20 lines
254 B
Plaintext
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read_verilog -sv <<EOT
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module doubleslash
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(input logic a,
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input logic b,
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output logic z);
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logic \a//b ;
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assign \a//b = a & b;
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assign z = ~\a//b ;
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endmodule : doubleslash
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EOT
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hierarchy
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proc
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opt -full
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write_verilog doubleslash.v
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