2019-10-18 05:19:59 -05:00
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read_verilog ../common/fsm.v
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2019-10-04 02:53:54 -05:00
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hierarchy -top fsm
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2019-09-03 03:53:37 -05:00
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proc
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flatten
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2019-11-11 08:41:33 -06:00
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equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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2019-09-03 03:53:37 -05:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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2019-10-04 02:53:54 -05:00
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cd fsm # Constrain all select calls below inside the top module
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2019-11-11 08:41:33 -06:00
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2019-09-04 04:15:52 -05:00
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select -assert-count 1 t:L6MUX21
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2019-11-11 08:41:33 -06:00
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select -assert-count 15 t:LUT4
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select -assert-count 6 t:PFUMX
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select -assert-count 6 t:TRELLIS_FF
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2019-09-04 04:15:52 -05:00
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select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
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