mirror of https://github.com/YosysHQ/yosys.git
9 lines
194 B
Verilog
9 lines
194 B
Verilog
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module aldffe( input [0:3] d, input [0:3] ad, input clk, aload, en, output reg [0:3] q );
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always @( posedge clk, posedge aload)
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if (aload)
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q <= ad;
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else
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if (en)
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q <= d;
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endmodule
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