mirror of https://github.com/YosysHQ/yosys.git
26 lines
536 B
Verilog
26 lines
536 B
Verilog
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/*
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Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
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*/
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module top(clk,a,b,c,set);
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parameter A_WIDTH = 4;
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parameter B_WIDTH = 3;
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input set;
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input clk;
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input signed [(A_WIDTH - 1):0] a;
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input signed [(B_WIDTH - 1):0] b;
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output signed [(A_WIDTH + B_WIDTH - 1):0] c;
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reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
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assign c = reg_tmp_c;
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always @(posedge clk)
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begin
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if(set)
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begin
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reg_tmp_c <= 0;
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end
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else
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begin
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reg_tmp_c <= a * b + c;
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end
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end
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endmodule
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