yosys/techlibs/xilinx/example_basys3/run_yosys.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog example.v
synth_xilinx -edif example.edif -top example
Added Xilinx example for Basys3 board 2015-02-01 10:09:34 -06:00			`read_verilog example.v`
			`synth_xilinx -edif example.edif -top example`