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yosys/tests/opt/opt_lut.ys

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opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-04 18:23:22 -06:00
read_verilog opt_lut.v
synth_ice40
ice40_unlut
design -save preopt
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 09:26:40 -06:00
opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-04 18:23:22 -06:00
design -stash postopt
design -copy-from preopt -as preopt top
design -copy-from postopt -as postopt top
equiv_make preopt postopt equiv
techmap -map ice40_carry.v
prep -flatten -top equiv
equiv_induct
equiv_status -assert