mirror of https://github.com/YosysHQ/yosys.git
14 lines
471 B
Verilog
14 lines
471 B
Verilog
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module bug3670(input we, output [31:0] o1, o2, output o3);
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// Completely missing port connections, where first affected port
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// (ADDRARDADDR) has a $setup delay
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RAMB36E1 ram1(.DOADO(o1));
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// Under-specified input port connections (WEA is 4 bits) which
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// has a $setup delay
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RAMB36E1 ram2(.WEA(we), .DOADO(o2));
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// Under-specified output port connections (DOADO is 32 bits)
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// with clk-to-q delay
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RAMB36E1 ram3(.DOADO(o3));
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endmodule
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